Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit.
Certain improvements in the performance of MOS ICs can be realized by forming the MOS transistors in a thin layer of semiconductor material (semiconductor layer) overlying a buried insulator layer that overlies a silicon substrate. Such semiconductor or silicon on insulator (SOI) MOS transistors, for example, exhibit lower junction capacitance and can operate at higher switching speeds than MOS transistors formed in bulk substrates. In SOI MOS transistors, the semiconductor layer, in which the source and drain regions are formed, is dielectrically encapsulated. In particular, the MOS transistors are typically enclosed in an interlayer dielectric material that overlies the semiconductor layer, which overlies the buried insulating layer. This configuration provides significant advantages but also give rise to certain issues.
One issue, especially in high performance devices such as microprocessors and the like, is that a thorough temperature sensing regime may be required across the substrate for device-internal temperature management because the buried insulating layer reduces the heat dissipation capabilities of the SOI devices. Temperature sensing can be accomplished using substrate contacts, for example, to form substrate diodes that are used to monitor the substrate temperature.
Typically, the substrate contacts are formed in the IC during the formation of the device contacts, which electrically couple to the source and drain regions of the MOS transistors. In one example, the device contacts are formed by etching a first set of trenches through the interlayer dielectric material to the source and drain regions of the MOS transistors, which are disposed in the semiconductor layer of the SOI substrate, and filling the first set of trenches with a conductive material. The substrate contacts are formed contemporaneously with the device contacts by etching a second set of trenches through the interlayer dielectric material to the silicon substrate, e.g., metal silicide region(s) disposed in the silicon substrate for improved electrical contact, and filling the second set of trenches with the conductive material. Because the silicon substrate is below the semiconductor and buried insulating layers of the SOI substrate, the formation of the second set of trenches requires a deeper etch through the interlayer dielectric material than for the first set of trenches. This deeper interlayer dielectric material etch can be more challenging and sometimes results in the formation of substrate contacts that marginally extend to the silicon substrate, which can negatively impact the performance and robustness of the substrate contacts.
Accordingly, it is desirable to provide methods for fabricating integrated circuits having substrate contacts with improved robustness, and integrated circuits fabricated by such methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.